Vertical memory devices having charge storage layers with thinned portions
US9741735B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 12, 2016 |
| Grant date | Aug 22, 2017 |
| Priority date | — |
| Expiry date | Jan 12, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/27
Abstract
A semiconductor device includes a stack comprising insulating patterns vertically stacked on a substrate and gate patterns interposed between the insulating patterns, an active pillar passing through the stack and electrically connected to the substrate and a charge storing layer interposed between the stack and the active pillar. The charge storing layer includes a first portion between the active pillar and one of the gate patterns, a second portion between the active pillar and one of the insulating patterns, and a third portion joining the first portion to the second portion and having a thickness less than that of the first portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.