Thin film transistor array panel and manufacturing method thereof
US9741748B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 6, 2016 |
| Grant date | Aug 22, 2017 |
| Priority date | — |
| Expiry date | Jan 17, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/021
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A thin film transistor array panel includes a substrate, a gate line and a gate pad disposed on the substrate, a gate insulating layer disposed on the gate line and the gate pad, a data line and a data pad disposed on the gate insulating layer, an organic layer disposed on the data line and the data pad, and a connecting member disposed on one of the gate pad and the data pad, in which the organic layer includes a first portion overlapping the connecting member and a second portion not overlapping the connecting member, and a height of the first portion of the organic layer is greater than a height of the second portion of the organic layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.