Patent · US Active

Flip-flop for reducing dynamic power

US9742382B2 · kind B2 · utility

7Cited by

9References

20Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventors

Yanfei Cai · Shanghai, CN
Qiang Dai · Suzhou, CN
Shuangqu Huang · Shanghai, CN

Key dates

Filing date	May 8, 2013
Grant date	Aug 22, 2017
Priority date	—
Expiry date	May 8, 2033

Classification

Technology area (CPC H)Electricity
CPC primaryH03K3/012
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A flip-flop circuit may include a first latch and a second latch. The first latch, which may operate as a “master” latch, includes a first input terminal to receive a data signal, a second input terminal to receive a clock signal, and an output terminal. The second latch, which may operate as a “slave” latch, includes a first input terminal connected directly to the output terminal of the first latch, a second input terminal to receive the clock signal, and an output terminal to provide an output signal. The first latch and the second latch are to be clocked on the same phase of the clock signal, thereby eliminating the need to include clock inversion circuits that generate complementary clock signals.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.