Serdes with high-bandwith low-latency clock and data recovery
US9742551B2 · kind B2 · utility
4Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 23, 2016 |
| Grant date | Aug 22, 2017 |
| Priority date | — |
| Expiry date | May 23, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M9/00
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The present application is directed to data communication. More specifically, embodiments of the present invention provide a SerDes system that includes multiple communication lanes that are aligned using a clock signal. Each of the communication lanes comprises a receiver, a buffer, and a transmitter. The receiver uses multiple sampling lanes for data sampling and clock recovery. Sampled data are stored at the buffer and transmitted by the transmitter. There are other embodiments as well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.