System and method for generating cascode current source bias voltage
US9746869B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 19, 2014 |
| Grant date | Aug 29, 2017 |
| Priority date | — |
| Expiry date | Aug 5, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F3/26
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A circuit includes: a cascode current source comprising: a current mirror transistor; and a cascode transistor; and a bias circuit coupled to the cascode current source, the bias circuit comprising: a current source; a first transistor coupled in series to the current source to form a first current path through the current source and the first transistor; a second transistor coupled in series to the current source; and a third transistor coupled in series to the second transistor and the current source to form a second current path through the current source and the second and third transistors, wherein the third transistor has a channel size greater than a channel size of the second transistor by a multiple determined according to a design factor of the bias circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.