Parallel pseudo random bit sequence generation with adjustable width
US9747076B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 2014 |
| Grant date | Aug 29, 2017 |
| Priority date | — |
| Expiry date | Aug 31, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/584
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Integrated circuits with pseudo random bit sequence (PRBS) generation circuitry are provided. The PRBS generation circuitry may be configured to support parallel output generation in multiple modes, where the parallel bit width in each mode can be different. The PRBS generation circuitry may include a linear feedback shift register that implements a desired polynomial, one or more XOR tree circuits that produces the parallel output bits, a multiplexer for selectively routing a subset of the parallel output bits back to the input of the shift register, and a gearbox for performing an adjustable bit width conversion. Configured in this way, the PRBS generation circuitry can provide parallel PRBS generation with an adjustable bit width.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.