Memory rank and ODT configuration in a memory system
US9747230B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 14, 2013 |
| Grant date | Aug 29, 2017 |
| Priority date | — |
| Expiry date | Jul 26, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1084
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes a two memory modules and a memory controller. The memory modules each include at least a first memory package corresponding to a first number of memory ranks (e.g. one memory rank) and a second memory package corresponding to a second number of memory ranks (e.g. two memory ranks) that is greater than the first number of memory ranks. For each module, the memory packages may be asymmetrically staggered such that one memory package is further from the memory controller than the other memory package. The memory controller is coupled to the memory packages of both modules via a common data line and generates control information for controlling the on-die termination (ODT) of the memory packages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.