Neural network processor
US9747546B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 3, 2015 |
| Grant date | Aug 29, 2017 |
| Priority date | — |
| Expiry date | Dec 22, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N5/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit for performing neural network computations for a neural network comprising a plurality of neural network layers, the circuit comprising: a matrix computation unit configured to, for each of the plurality of neural network layers: receive a plurality of weight inputs and a plurality of activation inputs for the neural network layer, and generate a plurality of accumulated values based on the plurality of weight inputs and the plurality of activation inputs; and a vector computation unit communicatively coupled to the matrix computation unit and configured to, for each of the plurality of neural network layers: apply an activation function to each accumulated value generated by the matrix computation unit to generate a plurality of activated values for the neural network layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.