Multi-channel memory system using asymmetric channel frequency scaling and related power management method
US9747963B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 3, 2014 |
| Grant date | Aug 29, 2017 |
| Priority date | — |
| Expiry date | Aug 6, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-channel memory system has a memory device, a plurality of channels, and a control circuit. The memory device has a plurality of memory storage spaces. The channels are coupled to the memory storage spaces, respectively, wherein each of the channels is configured to act as a memory interface for accessing a corresponding memory storage space independently. The control circuit controls clock frequencies of clocks on the channels, respectively. At a same time point, the channels include at least a first channel operating at a first clock frequency set by the control circuit and a second channel operating at a second clock frequency set by the control circuit at a same time point, and the second clock frequency is different from the first clock frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.