Chip to wafer package with top electrodes and method of forming
US9748162B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 6, 2015 |
| Grant date | Aug 29, 2017 |
| Priority date | — |
| Expiry date | Jan 6, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/12042
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip package and a method for forming the same are provided. The method includes: providing a first chip, wherein the first chip comprises a first surface and a second surface, and a first plurality of pads are disposed on the first surface; providing a second chip, wherein the second chip comprises a third surface and a fourth surface, a second plurality of pads are disposed on the third surface; combining the second surface of the first chip and the third surface of the second chip, wherein the second plurality of pads are out of the combination area of the first chip and the second chip; and forming a first insulation layer, wherein the first insulation layer covers the first chip, and is combined with the second chip. Processes of the method are simple, and the chip package is small.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.