Semiconductor devices having dummy patterns and methods of fabricating the same
US9748257B2 · kind B2 · utility
16Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 8, 2015 |
| Grant date | Aug 29, 2017 |
| Priority date | — |
| Expiry date | Dec 8, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B53/50
Abstract
Provided are semiconductor devices and methods of fabricating the same. The semiconductor devices may include a substrate with a cell region and a peripheral region, a gate stack including gates stacked on the cell region of the substrate. At least one edge portion of the gate stack may have a staircase structure. The semiconductor devices may also include a channel that extend through the gate stack and is enclosed by a memory layer and at least two dummy patterns on the substrate. The at least two dummy patterns may be spaced apart from the gate stack and may be spaced apart from each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.