Thin film transistor array substrate having a gate electrode comprising two conductive layers
US9748282B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 26, 2015 |
| Grant date | Aug 29, 2017 |
| Priority date | — |
| Expiry date | May 26, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/124
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
Provided is a thin film transistor array substrate having at least one thin film transistor. The thin film transistor includes a semiconductor layer having a channel area with a first doping concentration on a substrate, a source-drain area disposed at opposite sides of the channel area and with a second doping concentration greater than the first doping concentration, and a substantially undoped area extending from the source-drain area. The substrate has a gate insulating layer on the semiconductor layer and a gate electrode disposed on the gate insulating layer and overlapping the channel area in at least some portions. The substrate has a source electrode and a drain electrode, each insulated from the gate electrode and electrically connected to the source-drain area. The gate electrode includes a first gate electrode layer and a second gate electrode layer, wherein the second gate electrode layer is thicker than the first gate electrode layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.