Method of fabricating multi-wafer image sensor
US9748308B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 26, 2016 |
| Grant date | Aug 29, 2017 |
| Priority date | — |
| Expiry date | May 26, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/811
Abstract
A method of fabricating an image system includes forming a first wafer that includes a first semiconductor substrate and a first interconnect layer. A pixel array is formed in an imaging region of the first semiconductor substrate and a first insulation-filled trench is formed in a peripheral circuit region of the first semiconductor substrate. Additionally, a second wafer is formed that includes a second semiconductor substrate and a second interconnect layer. A second insulation-filled trench is formed in a second semiconductor substrate, and the first wafer is bonded to the second wafer. A third interconnect layer of a third wafer is bonded to the second wafer. At least one deep via cavity is formed through the first and second interconnect layers and through the first and second insulation-filled trenches. The at least one deep via cavity is filled with a conductive material to form a deep via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.