Thin film transistor and method of manufacturing the same
US9748396B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 6, 2016 |
| Grant date | Aug 29, 2017 |
| Priority date | — |
| Expiry date | Dec 6, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F2201/123
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
As source and drain wiring, a base layer and a cap layer are each formed of a MoNiNb alloy film, and a low-resistance layer is formed of Cu. The resultant laminated metal film is patterned through one-time wet etching to form a drain electrode and a source electrode. Cu serving as a main wiring layer does not corrode because of being covered with a MoNiNb alloy having good corrosion resistance. Further, even when a protective insulating film including an oxide is formed by plasma CVD in an oxidizing atmosphere, Cu is not oxidized. With the wet etching, the sidewall taper angle of the laminated metal film can be controlled to 20 degrees or more and less than 70 degrees.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.