Double consecutive error correction
US9748977B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 18, 2016 |
| Grant date | Aug 29, 2017 |
| Priority date | — |
| Expiry date | Nov 18, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/616
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Described is a processor with a data storage structure operative to store data and a first error correction code that corresponds to the data. The processor further includes circuitry to compare the first and second error correction codes to obtain a comparison result. There are no errors in the data when the comparison result is equal to zero and there is at least one error in the data when the comparison result is not equal to zero. The circuitry corrects a single bit error of the data when the comparison result matches one of the unique combination of bit values of one of the plurality of bit groups in the generator matrix and corrects two consecutive data bits of the data when the comparison result corresponds to a predefined number of values as a result of an exclusive-or (XOR) operation performed on two consecutive bit groups of the generator matrix.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.