Method for producing a printed circuit board with multilayer sub-areas in sections
US9750134B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 5, 2014 |
| Grant date | Aug 29, 2017 |
| Priority date | — |
| Expiry date | Mar 5, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/063
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method for producing a printed circuit board (13, 15, 16) with multilayer subareas in sections, characterized by the following steps: a) providing at least one conducting foil (1, 1′) and application of a dielectric insulating foil (3, 3′) to at least one subarea of the conducting foil; b) applying a structure of conducting paths (4, 4′) to the insulating layer (3, 3′); c) providing one further printed circuit board structure; d) joining of the further printed circuit board structure with the conducting foil (1, 1′) plus insulating layer (3, 3′) and conducting paths (4, 4′) by interposing a prepreg layer (5, 85; 18, 18′), and e) laminating the parts joined in step d) under pressing pressure and heat; and a printed circuit board produced according to this method.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.