System and method for optical input/output arrays
US9753220B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 30, 2016 |
| Grant date | Sep 5, 2017 |
| Priority date | — |
| Expiry date | Jun 30, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04Q2213/1301
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
System and method embodiments are provided for optical I/O arrays for wafer scale testing. A wafer includes a plurality of dies of PIC chips. Each die includes a plurality of first and second optical I/O elements each configured to couple to a testing probe array. A row of I/O elements includes alternating ones of the first and second optical I/O elements. Each die also includes a first waveguide and a second waveguide coupling a first one of the first and second optical I/O elements to a second one of the first and second optical I/O elements, respectively. The first and second optical I/O elements configured such that the testing probe array couples to at least some of the first optical I/O elements from a first side of the PIC chip and couples to at least some of the second optical I/O elements from a second side of the PIC chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.