Memory controller, data storage device, and memory control method
US9753652B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 20, 2013 |
| Grant date | Sep 5, 2017 |
| Priority date | — |
| Expiry date | May 14, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
To reduce deterioration of non-volatile memory and write data at higher speed, writing data is stored in a ReRAM when a page utilization rate R is lower than a threshold Rth1 and/or the writing data is frequently-rewritten data. With an empty space Semp2 in the ReRAM being less than a threshold Sth (step S110), when the data in the ReRAM is infrequently-rewritten data and the page utilization rate R obtained if target data is stored in a flash memory 22 is equal to or higher than a threshold value Rth3 (steps S120 and S130), data of logical sectors contained in N logical page addresses stored in a transfer list is read from the ReRAM to be written to the flash memory (steps S140 to S160). These steps reduce deterioration of the flash memory and allow higher data writing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.