Register-type-aware scheduling of virtual central processing units
US9753770B2 · kind B2 · utility
2Cited by
2References
26Claims
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Key dates
| Filing date | Mar 16, 2015 |
| Grant date | Sep 5, 2017 |
| Priority date | — |
| Expiry date | Apr 4, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/5019
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method includes running multiple processing tasks on multiple physical processing cores that support general-purpose registers and special-purpose registers. Respective usage levels, with which the processing tasks use the special-purpose registers, are estimated. The physical processing cores are assigned to the processing tasks based on the estimated usage levels of the special-purpose registers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.