Memory device and reference circuit thereof
US9754639B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2015 |
| Grant date | Sep 5, 2017 |
| Priority date | — |
| Expiry date | Oct 30, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device is disclosed that includes memory cells, a reference circuit, and a sensing unit. Each of the memory cells is configured to store bit data. The reference circuit includes reference switches and reference storage units. The reference switches are disposed. A first reference storage unit of the reference storage units is configured to generate a first signal having a first logic state when a first reference switch the reference switches is turned on. A second reference storage unit of the reference storage units is configured to generate a second signal having a second logic state when a second reference switch of the reference switches is turned on. The sensing unit is configured to determine a logic state of the bit data of one of the memory cells according to the first signal and the second signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.