Memory device and system supporting command bus training, and operating method thereof
US9754650B2 · kind B2 · utility
4Cited by
26References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2016 |
| Grant date | Sep 5, 2017 |
| Priority date | — |
| Expiry date | Jun 21, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device and system supporting command bus training are provided. An operating method of the memory device includes entering into a command bus training mode, receiving a clock signal, a chip selection signal and a first command/address signal, generating an internal clock signal by dividing the clock signal, generating a second command/address signal by latching the first command/address signal at a rising edge or a falling edge of the internal clock signal when a chip selection signal is activated, and outputting the second command/address signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.