Master/slave control voltage buffering
US9754656B2 · kind B2 · utility
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3References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 28, 2013 |
| Grant date | Sep 5, 2017 |
| Priority date | — |
| Expiry date | May 2, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0812
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In some embodiments, disclosed herein are approaches for facilitating voltage controlled slaved (or replica) clock circuits such as voltage controlled delay lines (VCDLs) off of a master clock generator. In such systems, one or more control (or bias) voltages are generated to control a master clock generator such as a master DLL. One or more “slave” circuits may be controlled off of the master's control voltage so that their clocks replicate desired traits of the master clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.