Interconnect structure and method
US9754822B1 · kind B1 · utility
20Cited by
22References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 2, 2016 |
| Grant date | Sep 5, 2017 |
| Priority date | — |
| Expiry date | Mar 2, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/151
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for surrounding dielectric layers. The insert layer may be applied between two dielectric layers. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.