Stacked semiconductor apparatus, system and method of fabrication
US9754921B2 · kind B2 · utility
5Cited by
25References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 10, 2015 |
| Grant date | Sep 5, 2017 |
| Priority date | — |
| Expiry date | Apr 16, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19106
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked semiconductor apparatus and method of fabricating same are disclosed. The apparatus includes upper and lower semiconductor devices having a similar pattern of connection elements. When stacked connected the resulting plurality of semiconductor devices includes a serial connection path traversing the stack, and may also include parallel connection paths, back-side mounted large components, and vertical thermal conduits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.