Power gate placement techniques in three-dimensional (3D) integrated circuits (ICs) (3DICs)
US9754923B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 9, 2016 |
| Grant date | Sep 5, 2017 |
| Priority date | — |
| Expiry date | May 9, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1434
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Power gate placement techniques in three-dimensional (3D) integrated circuits (ICs) (3DICs) are disclosed. Exemplary aspects of the present disclosure contemplate consolidating power gating circuits or cells into a single tier within a 3DIC. Still further, the power gating circuits are consolidated in a tier closest to a voltage source. This closest tier may include a backside metal layer that allows a distance between the voltage source and the power gating circuits to be minimized. By minimizing the distance between the voltage source and the power gating circuits, power loss from routing elements therebetween is minimized. Further, by consolidating the power gating circuits in a single tier, routing distances between the power gating circuits and downstream elements may be minimized and power loss from those routing elements are minimized. Other advantages are likewise realized by placement of the power gating circuits according to exemplary aspects of the present disclosure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.