Pixel driver circuit
US9755010B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 3, 2014 |
| Grant date | Sep 5, 2017 |
| Priority date | — |
| Expiry date | Dec 3, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K2102/311
Abstract
A pixel driver circuit having only three conductive layers is described. The pixel driver circuit comprises a vertical driver transistor (26) spanning said three conductive layers, wherein a first of said conductive layers (22) on a first side of a middle conductive layer (32) provides a first source-drain connection (52) of said driver transistor, wherein a third of said conductive layers (34) on the opposite side of said middle conductive layer to said first conductive layer provides a gate connection (54) for said vertical driver transistor, and wherein said middle conductive layer provides a second source-drain connection (50) for said vertical driver transistor. The circuit also comprises a lateral switching transistor (30) with source-drain connections (44,46) in one of said three conductive layers. A dielectric layer (16, 20) is provided between said first and second conductive layers and between said second and third conductive layers, and wherein semiconductor material (18) is provided spanning said first and second source-drain connections of said vertical driver transistor. A pixel display element (12) is coupled to said first source-drain connection of said vertical dri…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.