Semiconductor device including buffer circuit and level shifter circuit, and electronic device including the same
US9755643B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2015 |
| Grant date | Sep 5, 2017 |
| Priority date | — |
| Expiry date | Dec 14, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
To provide a semiconductor device that inhibits unexpected output of a high-level signal immediately after the rise of a power supply voltage. The semiconductor device includes a first buffer circuit, a level shifter circuit, and a second buffer circuit. A first potential is supplied to the first buffer circuit, and a second potential is supplied to the level shifter circuit and the second buffer circuit; consequently, the semiconductor device returns to a normal state. When the semiconductor device returns to a normal state, the second potential is supplied, so that the potential of a node in the level shifter circuit increases. To utilize the increase in the second potential or suppress malfunction due to the increase in the potential, capacitors are provided in the level shifter circuit. This inhibits unexpected operation of a transistor in the level shifter circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.