Device including single wire interface and data processing system including the same
US9755821B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 17, 2016 |
| Grant date | Sep 5, 2017 |
| Priority date | — |
| Expiry date | Mar 17, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A master device communicates with a slave device through an asynchronous serial communications link. The master device includes a single pad configured to communicate a command frame including an address and a data frame including data with the slave device via a single wire; and a processing circuit configured to generate an oversampling clock signal from a clock signal, to perform a synchronization process for selecting one of a plurality of clock phases of the oversampling clock signal, and to perform a sampling process for sampling an each bit value included in the data frame transmitted from the slave device using a clock phase at the same position as the clock phase selected during the synchronization process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.