Monitoring packet residence time and correlating packet residence time to input sources
US9755932B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2014 |
| Grant date | Sep 5, 2017 |
| Priority date | — |
| Expiry date | Oct 20, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L47/562
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An output circuit, included in a device, may determine counter information associated with a packet provided via an output queue managed by the output circuit. The output circuit may determine that a latency event, associated with the output queue, has occurred. The output circuit may provide the counter information and time of day information associated with the counter information. The output circuit may provide a latency event notification associated with the output queue. An input circuit, included in the device, may receive the latency event notification associated with the output queue. The input circuit may determine performance information associated with an input queue. The input queue may correspond to the output queue and may be managed by the input circuit. The input circuit may provide the performance information associated with the input queue and time of day information associated with the performance information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.