Patent · US Active

Chip-integrated through-plating of multi-layer substrates

US9756730B2 · kind B2 · utility

1Cited by

4References

10Claims

0Family size

Assignee

OSRAM Opto Semiconductors GmbH · DE

Inventors

Andreas Klein · Bonn, DE
Eckhard Ditzel · Gelnhausen, DE
Frank Krüger · Könnern, DE
Michael Schumann · Stuttgart, DE

Key dates

Filing date	Oct 21, 2011
Grant date	Sep 5, 2017
Priority date	—
Expiry date	Oct 24, 2031

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY10T29/49002
WIPO fieldAudio-visual technology
WIPO sectorElectrical engineering

Abstract

A laminate and method for producing the laminate are provided for contacting at least one electronic component. An insulating layer is laminated between first and second metal layers electrically contacted to each other in at least one contact region. At least one recess in the contact region is generated with at least one embossing and/or bulging in the first metal layer. The distance between the two metal layers is reduced, such that dimensions of the embossing/bulging are sufficient for taking up the electronic component, which is inserted and connected into the embossing/bulging in a conductive manner therein. The electronic component is taken up in the embossing/bulging entirely with respect to its circumference and at least partly with respect to the height (H) of the electronic component. The laminate may be used as a circuit board, sensor, LED lamp, mobile phone component, control, or regulator.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.