Damage reduction method and apparatus for destructive testing of power semiconductors
US9759763B2 · kind B2 · utility
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1References
19Claims
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Key dates
| Filing date | Jul 27, 2012 |
| Grant date | Sep 12, 2017 |
| Priority date | — |
| Expiry date | Mar 28, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/52
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A device and method for limiting damage to a semiconductor device under test when the semiconductor device fails during a high current, or high power test is provided. The occurrence of a failure of the device under test is detected, and power applied to the semiconductor device is diverted through a parallel path element upon detection of failure of the semiconductor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.