Patent · US Active

Forcing a processor into a low power state

US9760158B2 · kind B2 · utility

2Cited by
28References
22Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJun 6, 2014
Grant dateSep 12, 2017
Priority date
Expiry dateJul 12, 2035

Classification

  • Technology area (CPC Y)Emerging Cross-Sectional Technologies
  • CPC primaryY02D30/50
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.