System and methods of a CPU-efficient cache replacement algorithm
US9760493B1 · kind B1 · utility
15Cited by
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20Claims
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Key dates
| Filing date | Mar 14, 2016 |
| Grant date | Sep 12, 2017 |
| Priority date | — |
| Expiry date | Mar 14, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/152
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of updating a cache data structure that includes first, second, and third queues includes the step of storing contents of a data item in a cache location in response to a read or write input/output operation (IO) that accesses the data item. If the data item is not tracked in any of the first, second, and third queues, the data item is added to the first queue with the cache location of the data item. On the other hand, if the data item is tracked in the second queue, the data item is added to the third queue with the cache location of the data item.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.