Patent · US Active

Floating-gate transistor array for performing weighted sum computation

US9760533B2 · kind B2 · utility

13Cited by

12References

12Claims

0Family size

Assignee

THE REGENTS ON THE UNIVERSITY OF MICHIGAN · US

Inventors

Laura Fick · Austin, US
David Theodore Blaauw · Austin, US
Dennis Sylvester · Ann Arbor, US
Michael B. Henry · Ann Arbor, US
David Fick · Austin, US

Key dates

Filing date	Aug 14, 2014
Grant date	Sep 12, 2017
Priority date	—
Expiry date	Oct 16, 2034

Classification

Technology area (CPC G)Physics
CPC primaryG11C16/10
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A weighted sum is a key computation for many neural networks and other machine learning algorithms. Integrated circuit designs that perform a weighted sum are presented. Weights are stored as threshold voltages in an array of flash transistors. By putting the circuits into a well-defined voltage state, the transistors that hold one set of weights will pass current equal to the desired sum. The current flowing through a given transistor is unaffected by operation of remaining transistors in the circuit.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.