Method for manufacturing a semiconductor structure having a passivated III-nitride layer
US9761438B1 · kind B1 · utility
2Cited by
2References
6Claims
0Family size
Assignee
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Key dates
| Filing date | May 8, 2014 |
| Grant date | Sep 12, 2017 |
| Priority date | — |
| Expiry date | May 10, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure comprising a layer of a III-N material and at least a portion of said layer being covered by a passivation layer, wherein the passivation layer comprises a first layer of SiN formed on said at least a portion of said III-N material layer and a second layer of SiN formed on said first layer of SiN; the first SiN layer having a first thickness and generating tensile stress in the structure and the second SiN layer having a second thickness and generating compressive stress in the structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.