Crystalline tile
US9761547B1 · kind B1 · utility
9Cited by
2References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 17, 2016 |
| Grant date | Sep 12, 2017 |
| Priority date | — |
| Expiry date | Oct 17, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/16225
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A system and method for vertically integrating heterogeneous devices into a 3D tile architecture are disclosed. The system uses high precision microelectronics fabrication techniques and known-good-die to achieve high yield to integrate devices to process radio frequency signals at microwave frequencies of approximately 300 MHz to 300 GHz and above. The inventive architecture is based on a high density of small diameter vias to manage the integrity of electrical interconnects and simplify electrical routing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.