Macro transistor devices
US9761585B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 6, 2017 |
| Grant date | Sep 12, 2017 |
| Priority date | — |
| Expiry date | Feb 6, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/099
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Macro-transistor structures are disclosed. In some cases, the macro-transistor structures have the same number of terminals and properties similar to long-channel transistors, but are suitable for analog circuits in deep-submicron technologies at deep-submicron process nodes. The macro-transistor structures can be implemented, for instance, with a plurality of transistors constructed and arranged in series, and with their gates tied together, generally referred to herein as a transistor stack. One or more of the serial transistors within the stack can be implemented with a plurality of parallel transistors and/or can have a threshold voltage that is different from the threshold voltages of other transistors in the stack. Alternatively, or in addition, one or more of the serial transistors within the macro-transistor can be statically or dynamically controlled to tune the performance characteristics of the macro-transistor. The macro-transistors can be used in numerous circuits, such as varactors, VCOs, PLLs, and tunable circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.