Method for manufacturing array substrate, array substrate and display device
US9761617B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jan 14, 2016 |
| Grant date | Sep 12, 2017 |
| Priority date | — |
| Expiry date | Jan 14, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F2201/123
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method for manufacturing an array substrate comprises: forming a pixel electrode and a gate of a thin film transistor on a substrate; forming a gate insulating layer; forming an active layer and a source and a drain, which are provided on the active layer, of the thin film transistor by a patterning process; forming a passivation layer; forming a main via penetrating through the gate insulating layer and the passivation layer and a main-via extension portion under a portion of the drain by a patterning process, wherein the main via is connected to the main-via extension portion; removing a portion of the drain which protrudes above the main-via extension portion so as to form a final via; and forming a connection electrode and a common electrode, wherein the connection electrode electrically connects the drain to the pixel electrode through the final via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.