Synchronizing parallel power switches
US9762114B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 17, 2014 |
| Grant date | Sep 12, 2017 |
| Priority date | — |
| Expiry date | Jul 2, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/28
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The invention generally relates to methods and circuits for controlling switching of parallel coupled power semiconductor switching devices (3), for example for use in a power converter. In an example, there is provided a circuit for controlling switching of parallel coupled power semiconductor switching devices (3), the circuit comprising: a plurality of drive modules (2), each said module for controlling a said power semiconductor switching device (3); control circuitry to transmit switch command signals to the modules, each said switch command signal to trigger a said drive module to control a said power semiconductor switching device to switch state; and voltage isolation between the drive modules and the control circuitry, wherein each said drive module for controlling a said device comprises: timing circuitry (22) to compare a switching delay of the device and a reference delay, wherein said switching delay is a time interval between detecting a said switching command signal at the drive module and switching of the device in accordance with the detected switching command signal; and delay circuitry (21) to provide a controllable delay to delay a said triggering by a said swit…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.