Flip-flop circuit
US9762214B2 · kind B2 · utility
2Cited by
13References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 30, 2015 |
| Grant date | Sep 12, 2017 |
| Priority date | — |
| Expiry date | Jun 30, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356173
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A flip-flop circuit includes an evaluation part connected to a first node and a second node to discharge the second node according to a voltage level of the first node, a conditional delay part connected to the second node to discharge a third node to have a voltage level different from a voltage level of the second node, and a keeper logic part connected to the second node and third node to maintain a voltage level of one of the second and third nodes being not discharged.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.