Cancellation of spurious tones within a phase-locked loop with a time-to-digital converter
US9762250B2 · kind B2 · utility
16Cited by
7References
33Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 31, 2014 |
| Grant date | Sep 12, 2017 |
| Priority date | — |
| Expiry date | Jul 31, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/3004
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase-locked loop (PLL) includes a spur cancellation circuit that receives a residue signal indicative of a first frequency and receives a residual phase error signal and generates a spur cancellation signal. A summing circuit combines the spur cancellation signal and a first phase error signal corresponding to a phase difference between a reference signal and a feedback signal in the PLL and generates a second phase error signal with a reduced spurious tone at the first frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.