System and method for self-interference suppression structure
US9762299B1 · kind B1 · utility
0Cited by
4References
17Claims
0Family size
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Key dates
| Filing date | Mar 3, 2016 |
| Grant date | Sep 12, 2017 |
| Priority date | — |
| Expiry date | Mar 3, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/525
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A tapped delay line channel model may be employed to suppress the self-interference that is introduced, at a receiver input, by a signal at a transmitter output. The self-interference may be considered to have components introduced by the internal antenna subsystem of a full duplex MIMO transceiver.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.