Chroma cache architecture in block processing pipelines
US9762919B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 28, 2014 |
| Grant date | Sep 12, 2017 |
| Priority date | — |
| Expiry date | Apr 22, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6026
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus for caching reference data in a block processing pipeline. A cache may be implemented to which reference data corresponding to motion vectors for blocks being processed in the pipeline may be prefetched from memory. Prefetches for the motion vectors may be initiated one or more stages prior to a processing stage. Cache tags for the cache may be defined by the motion vectors. When a motion vector is received, the tags can be checked to determine if there are cache block(s) corresponding to the vector (cache hits) in the cache. Upon a cache miss, a cache block in the cache is selected according to a replacement policy, the respective tag is updated, and a prefetch (e.g., via DMA) for the respective reference data is issued.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.