Pixel array area optimization using stacking scheme for hybrid image sensor with minimal vertical interconnects
US9763566B2 · kind B2 · utility
23Cited by
334References
34Claims
0Family size
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Key dates
| Filing date | Aug 31, 2015 |
| Grant date | Sep 19, 2017 |
| Priority date | — |
| Expiry date | Nov 25, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F77/124
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of a hybrid imaging sensor that optimizes a pixel array area on a substrate using a stacking scheme for placement of related circuitry with minimal vertical interconnects between stacked substrates and associated features are disclosed. Embodiments of maximized pixel array size/die size (area optimization) are disclosed, and an optimized imaging sensor providing improved image quality, improved functionality, and improved form factors for specific applications common to the industry of digital imaging are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.