Wafer-level testing of photonic integrated circuits with optical IOs
US9766410B1 · kind B1 · utility
7Cited by
1References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 10, 2015 |
| Grant date | Sep 19, 2017 |
| Priority date | — |
| Expiry date | Jul 10, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02B2006/12159
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
Techniques for forming a photonic integrated circuit having a facet coupler and a surface coupler are described. The photonic integrated circuit may be on a wafer, which may be diced to form an integrated device. The facet coupler may be positioned proximate to an edge of the integrated device, and the surface coupler may be positioned on a surface of the integrated device. The surface coupler may allow for evaluation and assessment of the circuit's performance, which may facilitate wafer-level testing of the circuit and diagnosis of the circuit before and after packaging.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.