Array substrate, manufacturing method thereof, display panel and display device
US9766520B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 18, 2015 |
| Grant date | Sep 19, 2017 |
| Priority date | — |
| Expiry date | Aug 1, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F2201/50
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
The invention discloses array substrate, manufacturing method thereof, display panel and display device, array substrate comprises TFTs, common electrodes, common electrode lines, data lines and gate lines, each TFT comprises gate, active layer corresponding to the gate, protective layer corresponding to the gate line or gate, and ESL, the active layer and protective layer are provided in the same layer and separated from each other; the ESL is provided with source holes and drain hole corresponding to the active layer, protective hole corresponding to the protective layer but not overlapping with the data line, and connecting holes corresponding to the common electrode and common electrode line; and distance between each connecting hole and the protective hole closest thereto is smaller than that between the connecting hole and the source or drain hole closest thereto, and/or, diameter of said protective hole is smaller than those of the source and drain holes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.