Checksum adder
US9766859B2 · kind B2 · utility
2Cited by
2References
1Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 7, 2016 |
| Grant date | Sep 19, 2017 |
| Priority date | — |
| Expiry date | Nov 7, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments relate to a hardware circuit that is operable as a fixed point adder and a checksum adder. An aspect includes a driving of a multifunction compression tree disposed on a circuit path based on a control bit to execute one of first and second schemes of vector input addition and a driving of a multifunction adder disposed on the circuit path based on the control bit to perform the one of the first and second schemes of vector input addition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.