Memory controller and memory system including the same
US9767053B2 · kind B2 · utility
3Cited by
6References
27Claims
0Family size
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Key dates
| Filing date | Dec 11, 2013 |
| Grant date | Sep 19, 2017 |
| Priority date | — |
| Expiry date | Jul 27, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller connected with a storage medium via a plurality of channels is provided which includes a signal processing block including a plurality of signal processing engines; and a decoding scheduler configured to control a data path such that at least one activated signal processing engine of the plurality of signal processing engines is connected with the plurality of channels, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.