Low power parallelization to multiple output bus widths
US9767062B2 · kind B2 · utility
0Cited by
4References
20Claims
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Key dates
| Filing date | Apr 17, 2015 |
| Grant date | Sep 19, 2017 |
| Priority date | — |
| Expiry date | Dec 1, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A Serializer/Deserializer (SerDes) is described with an architecture that simultaneously provides flexibility for many different gear ratios as well as reduced power consumption. The SerDes utilizes latches where flops were previously used to help reduce power consumption, among other things. The SerDes also includes a main register bank with a plurality of sub-banks that can be filled according to any number of different schemes, thereby enabling the SerDes to accommodate different output widths.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.