Semiconductor having cross coupled structure and layout verification method thereof
US9767248B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 3, 2015 |
| Grant date | Sep 19, 2017 |
| Priority date | — |
| Expiry date | Sep 8, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/333
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device and a layout verification method of a semiconductor device are provided. The layout verification method includes forming a plurality of standard cells each having a first type of a cross coupled structure (XC) and a second type of the XC on a substrate of the semiconductor device, forming a plurality of first inverters in which the first type of the XC is activated in the a plurality of the standard cells and a plurality of second inverters in which the second type of the XC is activated in the a plurality of the standard cells and estimating an electrical characteristic of the first type of the XC or the second type of the XC by measuring a magnitude of a signal delay of the plurality of the first inverters or the plurality of the second inverters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.